This invention relates to a semiconductor memory device, especially to a semiconductor mask read only memory device with a high speed read cycle.
Generally, there are two types of read only memory (ROM) which may be used as the storage device of a digital computer. One is a programmable read only memory (PROM) which can be programmed when it is used, and the other is a mask ROM which is programmed during the manufacturing process.
In recent years, in accordance with the miniaturization and the speed up of the computer, it is required to integrate a mask ROM used for storing a computer program etc. on a larger scale and to speed up its read out time.
In FIG. 1, a prior art semiconductor mask ROM is illustrated. The mask ROM of FIG. 1 comprises a load transistor of a depletion type Q.sub.L, a multiplexer MPX consisting of a plurality of transistors Q.sub.x0, Q.sub.x1 . . . Q.sub.xn to the gates of which the address selecting signals A.sub.0, A.sub.1 . . . A.sub.n are respectively applied, a memory cell array having transistors Q.sub.ij (i=0, 1 . . . m, j=0, 1 . . . n) with gates connected to the word lines WL.sub.0, WL.sub.1 . . . WL.sub.m, and a gate transistor Q.sub.G inserted between the load transistor Q.sub.L and the multiplexer MPX. The ROM of FIG. 1 is used for example in the one chip microprocessor MC6801 manufactured by MOTOROLA Corporation.
As shown in FIG. 1, the gate of the gate transistor Q.sub.G is supplied with the output signal of a voltage control circuit CNT. In the voltage control circuit CNT, a depletion type transistor Q.sub.c1 and transistors Q.sub.c2 and Q.sub.c3 are connected in series between the voltage source V.sub.cc and ground. The voltage V(N.sub.0) at the node N.sub.0 where the load transistor Q.sub.L and the gate transistor Q.sub.G are connected, is supplied to the data bus line DB through the buffer circuit BUF as shown. In the buffer circuit BUF, there are provided gate circuits GT.sub.1, GT.sub.2 and transistors Q.sub.B1, Q.sub.B2 interconnected as shown in FIG. 1.
The transistors Q.sub.x0, Q.sub.x1 . . . Q.sub.xn of the multiplexer MPX, are connected to the bit lines BL.sub.0, BL.sub.1 . . . BL.sub.n respectively, the transistor Q.sub.ij (i=0, 1 . . . m, j=0, 1 . . . n) of the memory cell array corresponds to the word line WL.sub.i and the bit line BL.sub.j. The gate of the transistor Q.sub.ij is connected to the word line WL.sub.i and its source is connected to the ground. The drain of the transistor Q.sub.ij is connected to the bit line BL.sub.j when the data "0" is stored in the memory cell of the transistor Q.sub.ij, and the drain of the transistor Q.sub.ij is disconnected from the bit line BL.sub.j when the data "1" is stored in this memory cell.
The read operation in the ROM of FIG. 1 is as follows. The ROM of FIG. 1 has two operation modes, one mode is the preparation operation for reading and the other mode is the reading operation. In the preparation operation for reading all selecting signals A.sub.0, A.sub.1 . . . A.sub.n of the multiplexer MPX and all word lines WL.sub.0, WL.sub.1 . . . WL.sub.m are set to the "H" level. Therefore, all transistors Q.sub.ij of the memory cell array MCA become conductive and consequently the charge accumulated in the stray capacity of each bit line BL.sub.0, BL.sub.1 . . . BL.sub.n is discharged through the transistors Q.sub.ij connected to the bit line BL.sub.j and the potentials at the bit lines BL.sub.0, BL.sub.1 . . . BL.sub.n decrease to the ground level. According to the decrease of the potentials at the bit lines BL.sub.0, BL.sub.1 . . . BL.sub.n, the charge accumulated in the stray capacity of the node N.sub. 0 is discharged through the gate transistor Q.sub.G and the transistors Q.sub.x0, Q.sub.x1 . . . Q.sub.xn of the multiplexer MPX. Therefore, the potential at the node N.sub.0 goes to the "L" level.
Then, in the reading operation, in order to read the data stored in a certain memory cell, one of the selecting signals A.sub.0, A.sub.1 . . . A.sub.n and one of the word lines WL.sub.0, WL.sub.1 . . . WL.sub.m are kept at the "H" level, and the other selecting signals and the other word lines are set to the "L" level. For example, in the case of reading the memory cell of the transistor Q.sub.01, only the selecting signal A.sub.1 and the word line WL.sub.0 are kept at the "H" level, and the other selecting signals A.sub.0, A.sub.2 . . . A.sub.n and the other word lines WL.sub.1, WL.sub.2 . . . WL.sub.m are set to the "L" level. In this case, only the transistor Q.sub.x1 is conductive and all the other transistors Q.sub.xj of the multiplexer MPX are non-conductive. Among the transistors Q.sub.i1 of bit line BL.sub.1, only the transistor Q.sub.01 is conductive and the other transistors Q.sub.j1 are non-conductive. As the transistor Q.sub.01 is connected to the bit line BL.sub.1, the current supplied from the voltage source V.sub.cc flows through transistors Q.sub.L, Q.sub.G, Q.sub.x1 and Q.sub.01 to ground, and therefore the charge is not accumulated in the stray capacity of the node N.sub.0 and the potential at the node N.sub.0 is held at the "L" level. Accordingly, the data of "L" level (that is "0") is transmitted to the data bus line DB through the buffer circuit BUF.
Then, in the case of reading the memory cell of the transistor Q.sub.11, only the selecting signal A.sub.1 and the word line WL.sub.1 are held to the "H" level. Accordingly, among the transistors of the multiplexer MPX only Q.sub.x1 is conductive and among the transistors of the bit line BL.sub.1 only Q.sub.11 is conductive. In this case, the transistor Q.sub.11 is disconnected from the bit line BL.sub.1 so that the bit line BL.sub.1 is disconnected from ground. Therefore, the current supplied from the voltage source V.sub.cc flows into the stray capacity of the bit line BL.sub.1 through transistors Q.sub.L, Q.sub.G and Q.sub.x1, and the capacity is charged by this current. Thus, the potentials at the bit line BL.sub.1 and the node N.sub.0 rises up and reach the "H" level. This "H" level signal of the node N.sub.0 is transmitted to the data bus DB through the buffer circuit BUF.
However, in the ROM of FIG. 1, together with the increase in the memory capacity and the integration scale of a memory device, the size of the transistor Q.sub.ij of the memory cell becomes smaller, so that the resistance of the main current path of the transistor Q.sub.ij becomes greater. Since the output signal level of the node N.sub.0 in the case of reading "L" level data, is mainly determined by the ratio between the resistors of the memory cell transistor Q.sub.ij and the load transistor Q.sub.L, in order to obtain an appropriate output signal level, it is necessary to make the resistance of the load transistor Q.sub.L proportionally greater. However, since in accordance with the increase in the resistance of the main current path of the load transistor Q.sub.L, the drive capacity of the load transistor Q.sub.L decreases, it takes a relatively longer time to charge the bit lines having an equivalently large capacity, and to raise the potential to the "H" level.
In order to prevent an increase in the access time of the memory device due to the above-mentioned decrease in the drive capacity of the load transistor Q.sub.L, in accordance with the ROM of FIG. 1 the gate transistor Q.sub.G is provided. The function of the gate transistor Q.sub.G in the above-mentioned reading operation of the memory cell transistor Q.sub.11 will now be described. As described above, in the reading operation of the transistor Q.sub.11, the charge accumulated in the stray capacity of the bit line BL.sub.1 is supplied from the voltage source V.sub.cc through the load transistor Q.sub.L, the gate transistor Q.sub.G and the transistor Q.sub.x1 of the multiplexer MPX. The output signal V.sub.INT of the gate voltage control circuit CNT is applied to the gate of the gate transistor Q.sub.G, and if the potential at the node N.sub.1 connected to the source of the gate transistor Q.sub.G is lower than the level of the signal V.sub.INT, the resistance of the main current path of the gate transistor Q.sub.G is relatively small, and therefore the potential at the bit line BL.sub.1 rises gradually according to the drive capacity of the load transistor Q.sub.L. In accordance with this , the potentials at the nodes N.sub.0 and N.sub.1 also rise, and when the difference, between the potentials at the gate of the gate transistor Q.sub.G and at the node N.sub.1, is below the threshold voltage V.sub.TH of the gate transistor Q.sub.G, the gate transistor Q.sub.G is turned into the cut-off state, so that the bit line BL.sub.1 and the node N.sub.1 are separated from the node N.sub.0. Therefore, the potential at the node N.sub.0 which has been rising gradually in accordance with the potential at the bit line BL.sub.1, then rises rapidly and goes to the "H" level.
As described above, in accordance with the ROM of FIG. 1, since the stray capacity of the bit line BL.sub.j is separated from the node N.sub.0 by means of the gate transistor Q.sub.G, in spite of the small drive capacity of the load transistor Q.sub.L, an increase in the access time of the memory cell can be prevented. However, since the gate voltage of the gate transistor Q.sub.G is between the voltage source V.sub.cc and ground level, the resistance value of the gate transistor Q.sub.G as a resistance element is relatively great. Therefore, in the ROM of FIG. 1, although the reading operation time becomes shorter, there is a problem in that it takes a rather long time to decrease the potential at the node N.sub.0 to the "L" level in the preparation operation for reading.